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Renesas Electronics /R7FA6E2BB /CEC /CECEXMD

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Interpret as CECEXMD

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7 43 0 0 00 0 0 0 0 0 0 0 0 (0)LERPLEN 0 (0)RERCVEN 0 (0)RCVINTDSEL

RCVINTDSEL=0, RERCVEN=0, LERPLEN=0

Description

CEC Extension Mode Register

Fields

LERPLEN

Pulse Output Function Enable by Long Bit Width Error

0 (0): Detects only a long bit width error.

1 (1): Detects a long bit width error and outputs an error handling pulse.
RERCVEN

Start Detection Reception Restart Enable

0 (0): Does not restart reception when the start bit is detected during reception.

1 (1): Restarts reception when the start bit is detected during reception.
RCVINTDSEL

INTDA Reception Interrupt Timing Change

0 (0): EOM timing (9th bit of data)

1 (1): ACK timing (10th bit of data)

Links

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Register License

This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all applicable laws, including copyright laws.

THIS SOFTWARE IS PROVIDED “AS IS” AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data